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uart_test
- 描述了利用spatran6系列的FPGA，进行串行异步通信的uart串口实现代码(Describes the use of spatran6 series of FPGA, serial asynchronous communication uart serial port to achieve the code)
uart
- UART的串口程序，收发功能都已实现，直接可用(UART serial procedures, transceiver functions have been achieved, directly available)
UART1
- 基于Verilog的串口RS232控制器(RS232 controller of serial port based on Verilog)
ad7606
- AD7606采集代码，用于verilog 驱动 AD7606 adc SPI 串口方式(AD7606 acquisition code, used for Verilog drive AD7606 ADC SPI serial mode)
SPI协议的Verilog_实现
- spi串口原理介绍，并附有verilog编程代码，有助于在FPGA上实现。(The principle of SPI serial, and with a Verilog programming code, contribute to the implementation on FPGA.)
uart-master
- verilog语言实现URAT串口通信，便捷开发(Implementation of various basic circuits in digital circuits with Verilog language)
help_lib
- 1.JESD204B协议 2.Xilinx的JESD204B phy 核手册 3.Xilinx的JESD204B rx_tx 核手册7.1 4.Xilinx的JESD204B rx_tx 核手册7.2 5.verilog实现串口发送(1.JESD204B protocol 2.Xilinx JESD204B PHY core manual 3.Xilinx JESD204B rx_tx core manual 7.1 4.Xilinx JESD204B rx_tx core man
uart
- 一个具有固定波特率的 UART 串口收发器，可以实现 串口收发器，可以实现 9600 波特率的串口通信， 能够与 PC 机串口进行通信，支持 8 比特数据位、 1 比特停止位、无校验硬件流控模式(A fixed baud rate UART serial transceiver, can realize serial transceiver, can achieve 9600 baud rate serial communication, and can communicate with PC
uart_test
- 通过FPGA，实现串口传输数据，并且可以支持多种不同的波特率，用EP4CE22F17芯片实现。(Through the FPGA, serial transmission data, and can support a variety of baud rates, using EP4CE22F17 chip implementation.)
vga_7_0728
- 用vga显示数字钟，通过串口可以控制时间显示(With vga digital clock, through the serial port can control the time display)
8_uart_test
- 串口通信，基于Quartus的用Verilog实现串口通信(Serial communication and serial communication with Verilog based on Quartus)
my_sdram_mdl
- 此功能为altera fpga 的sdram 控制器，串口接收与发送(This feature altera fpga sdram controller, serial port to receive and send)
test_uart
- 该资料包含用FPGA（EP4CE22F17型号）编写的UART通信程序，最重要的是里面含有串口波特率可调，包括一些常见的波特率。(This information includes UART communication program written by FPGA (EP4CE22F17 model), and most importantly, it contains serial port baud rate tunable, including some common baud rate
spi_master
- SPI通信：串行flash的读写擦除命令通过SPI接口进行通信。? CPU芯片与FPGA通过SPI接口进行通信。? 其他功能集成电路芯片参数寄存器配置。例如DAC芯片内部有很多寄存器（因为芯片有很多功能，要通过设置寄存器不同的开关来打开或关闭相应的功能，一上电去初始化寄存器）需要我们去配置。FPGA一上电也是通过配置芯片里边来读取数据，然后配置FPGA内部的SRAM。FPGA是读取FLASH里边的串行数据，读取完校验完才配置到我们的FPGA的SRAM中去。速度比串口快，而且是同步传输。(Th
uart
- uart串口FPGA实现示例 example(uart serial interface example)
CPU-Pipeline
- 五级流水线的CPU的工程文件，在vivado上用verilog语言实现，包括串口，可进行简单的数学加法运算。(Five-stage pipeline CPU project files, including the serial port. vivado Verilog language. This CPU can do simple mathematical addition.)
uart_fifo_n
- verilog 带fifo的串口收发模块(verilog uart with fifo)
uart
- 用verilog实现UART串口收发。状态机形式实现，波特率可调(Use verilog to achieve UART serial transceiver. State machine form, adjustable baud rate)
UART发送接收奇偶校验
- 状态机，串口收发，以及奇偶校验。 even_parity.v奇偶校验； receive_byte.v字节接收； send_byte.v字节发送(state machine,UART even_parity.v even parity; receive_byte.v receiving byte; send_byte.v sending byte)
UartRecv
- 利用FPGA实现简单的串口接收驱动程序，actel。(Using FPGA to implement a simple serial port receiver driver, Actel)